Flip chip, or Controlled Collapse Chip Connection (C4), is a method for interconnecting semiconductor devices, such as integrated circuit chips and MEMS, to external circuitry with solder bumps that have been deposited onto the chip pads. The solder bumps are deposited on the chip pads on the topside of the wafer during the final wafer processing step. In order to mount the chip to external circuitry (e.g., a circuit board or another chip or wafer), it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is flowed to complete the interconnect.
Conventional flip-chip attachment methods using standard (ball-shaped) bumps suffer the following defects: 1) inconsistent gaps between die and substrate, 2) reduced pitch reduces the gap between die and substrate, 3) substrate solder mask opening variations change the gap, and 4) bump diameter variation causes inconsistent underfill.
In contrast, a pillar-bump flip-chip attachment method uses pillar-shaped bumps instead of ball-shaped bumps and has the following advantages: 1) consistent gaps between die and substrate (rigid-bump), 2) a fine pitch bump with no change in bump height, thus reduced die size, e.g., 80 μm fine pitch, 3) no solder mask (SM) eliminates SM-related defects, 4) consistent underfill with pillar-shape bumps, and 5) flexible pad locations—resolving critical design bottlenecks.
In particular, copper pillar solder bumps (CPB) have the following advantages: 1) better thermal/electric performance, 2) higher current carrying capacity, 3) better resistance to electromigration, thus longer bump life, 4) minimizing molding voids—i.e., more consistent gaps between Cu-pillar-bumps. Also, a lower cost substrate is possible by using Cu-pillar controlled solder spreading, eliminating lead-free teardrop design, and using fine-pitch maskless substrate and bare Cu pads. Further, CPB provides soft error protection for sensitive devices (e.g., memory chips), i.e., “Alpha emission” protection by Cu-pillar distance. A CPB also means that a lead-free pillar bump is available.
The presence of Cu in the solder also affects the adhesion of the Intermetallic Compound (IMC). In the Cu-containing solder alloy, the interfacial IMC (e.g., Sn—Cu—Ni) adheres to the electroless under-bump metal (UBM, e.g., Ni—P). Without Cu (e.g., Ni—Sn or Ni—Sn—Ag), the IMC (e.g., needle-type Ni3Sn4) loses adhesion and spalls off the electroless UBM interface (e.g., Ni—P).
However, there are concerns regarding the Intermetallic Compound (IMC) and Kirkendall void growth in Cu pillar bumps during annealing and current stressing. When used with Sn solder material, sufficient Cu supply from Cu pillar forms a thick IMC, such as Cu6Sn5 and Cu3Sn, through the reaction between Cu and Sn. Thick IMC layers reduce the mechanical strength of the Cu pillar bumps because IMCs are brittle. The IMC becomes scalloped and spalls off the interface. With thicker (e.g., 20 mm) Sn solder, longer annealing processes and an abundant Cu source make Cu3Sn thicker, and also the size of Cu6Sn5 becomes large. Total transfer of the ductile solder to harder IMC lowers the shear strength of the structure. Also, thicker IMC results in poor adhesion. Further, Kirkendall voids can develop at the pillar and Cu3Sn interface, resulting in a bad interface and poor contact between the Cu pillar and Cu3Sn.
Accordingly, new method and structure for good adhesion of Intermetallic Compound (IMC) on Cu pillar bumps and reliable structural integrity are desired.